1. Field of the Invention
The present invention relates to a clamp signal generation-control circuit and method therefor, and more particularly to a clamp signal generation-control circuit for discriminating a video signal supplied to a monitor to display a picture whether a sync signal is mixed with a green signal in the video signal and automatically controlling a clamp signal supplied in accordance with the result of the discrimination, and a method for embodying the same.
2. Description of the Prior Art
Picture output apparatuses of a monitor are generally referred as video cards. The video cards are variously provided according to types of the monitors employed.
Signals from the various video cards are such as red (hereinafter simply referred to as "R"), green (G) and blue (B) signals, and horizontal and vertical sync signals.
The horizontal/vertical sync signal supplied from the video card may be separated from the R, G and B signals, or mixed with the G signal. At this time, the signal resulting from nixing the horizontal/vertical sync signal with the G signal is named as "a sync on green signal", and the separately supplied signal to a horizontal/vertical sync signal output terminal is named as "a separate sync signal".
The horizontal sync signal in the separate sync signal is designated as H-SYNC and the vertical sync signal therein is designated as V-SYNC. A clamp signal is for clamping the video signal level. Here, the level clamped by the clamp signal is a position at which the video signal is fixed to 0 V.
FIG. 1 is general waveforms of the signals from the video card, in which respective waveforms represent only the R signal, only the G signal, only the B signal, the H-SYNC in the separate sync signal, the V-SYNC in the separate sync signal, and the sync on green signal showing the state that the H/V sync signal is mixed with the green signal.
The voltage levels of the R, G and B signals in FIG. 1 must be the same. However, if the H-SYNC and V-SYNC are mixed with the G signal, i.e., in case of the sync on green signal of FIG. 1, the voltage level thereof becomes different from those of R, G and B in FIG. 1. In other words, the voltage level of the sync on green signal is heightened as much as the voltage levels of the R, G and B in FIG. 1 loaded with the sync signal.
However, the voltage levels of the signals supplied as shown in FIG. 1 must be the same at any time. In order to constantly control the voltage levels of respective signals, the clamp signal is utilized, and a position of the sync on green signal from which the clamp signal is generated is a reference voltage, i.e., 0 V. That is, when the clamp signal is supplied from a point "a" of the sync on green signal, the potential of the point a is recognized as 0 V. Similarly, if it is supplied from a point "b", the potential thereof is recognized as 0 V.
At this time, the video signal is processed in the monitor, using the level recognized as 0 V as a reference.
Also, in accordance with the type of the sync signal received into the monitor, i.e., by determining the received sync signal whether it is the separate sync signal or sync on green signal, the clamp signal should be triggered at a front or back porch to be outwardly supplied, and then the video signal level is determined by the resultant output. Therefore, it is very important to supply the clamp signal fitted to the kind of the sync signal.
FIG. 2 is a circuit diagram showing a conventional clamp signal generation-control circuit. When the sync on green signal of FIG. 1 is received into a sync signal separating portion 10 via a green signal input terminal G, the sync signal is separated by means of an internally-preset reference voltage to be supplied to a sync signal selecting portion 11, and H-SYNC and V-SYNC are also supplied to the sync signal selecting portion 11.
At this time, the sync signal separating portion 10 may be supplied with only the G signal or the sync on green signal of FIG. 1. In the same manner, the H-SYNC and V-SYNC may or may not be received into the input side of the sync signal selecting portion 11.
If an output signal of the sync signal separating portion 10 and H/V SYNC signal are simultaneously supplied to the sync signal selecting portion 11, the H/V SYNC signal is primarily selected to be supplied to a clamp signal generating portion 12 and a H/V sync separating portion 13.
The clamp signal generating portion 12 triggers an edge of the sync signal selectively supplied from the sync signal selecting portion 11 to generate the clamp signal. Here, the generated clamp signal is mixed on the front or back portion of the sync signal, wherein the front and back portions are manually shifted by switching of a switching portion 14.
Meanwhile, the H/V sync separating portion 13 separates the H/V SYNC signal into the H-SYNC and V-SYNC, using a low-pass filter (not shown). The H-SYNC separated in the H/V sync separating portion 13 is supplied to the unshown monitor unchanged, and V-SYNC is supplied to an adder 15.
The adder 15 adds the V-SYNC from the H/V sync separating portion 13 to V-SYNC from the other side thereof to supply the resultant sum to the monitor.
FIG. 3 is a block diagram schematically showing a conventional clamp signal generation-control circuit similar to that shown in FIG. 2, wherein either the sync on green signal or a sync signal at a TTL (transistor transistor logic) level is selected to output the clamp signal.
To begin with, a sync signal in the sync on green signal received via a sync on green signal input portion 16 is solely separated in a sync signal separating portion 17, and then supplied to a sync signal selecting portion 18. First and second TTL level sync signals are supplied to a TTL level sync signal processing/mixing portion 21 via first and second TTL level sync signal input portions 19 and 20.
Here, the TTL level sync signal denotes a signal received at 0 V/5 V level under the low/high concept which is generally adopted in electronic circuitry. The first and second TTL level sync signals are two types of different sync signals supplied from respective main frames to the monitor when only one monitor is connected to two main frames in personal computers, etc.
The TTL level sync signal processing/mixing portion 21 manually selects to process either one of the first and second TTL level sync signals from the first and second TTL level sync signal input portions 19 and 20, using an unshown switch, and supplies a processed signal to the sync signal selecting portion 18.
The sync signal selecting portion 18 manually selects any one of the sync signals from the sync signal separating portion 17 and the TTL level sync signal processing/mixing portion 21, using the switch, and supplies a selected sync signal to a sync signal processing portion 22 which in turn constantly maintains a polarity of the received sync signal to supply it as a sync signal output and to a clamp signal generating portion 24. The clamp signal generating portion 24 generates the clamp signal triggered at the back porch of the received sync signal to supply it as a clamp signal output.
FIG. 4 is a detailed circuit diagram showing the clamp signal generating portion 12 of FIG. 2, wherein the H-SYNC from the sync signal selecting portion 11 of FIG. 2 is supplied to an input side of an exclusive OR gate 26, and a sync signal discriminating portion 27 discriminates a signal in response to a switching control signal from the switching portion 14 of FIG. 2 to supply a logic signal in accordance with the result of the discrimination to other side of the exclusive OR gate 26.
The exclusive OR gate 26 supplies a signal obtained by ORing a logic signal from the sync signal discriminating portion 27 and the H-SYNC to a multivibrator 28, and generates a predetermined frequency signal of which duty is determined in view of a time constant of a capacitor C and a resistor R connected to one side thereof.
The operation of the circuit shown in FIG. 4 will be described in detail with reference to FIG. 5.
The sync signal discriminating portion 27 generates a logic signal of low level when the signal supplied to the monitor is the sync on green signal, or a logic signal of high level when it is the separate sync signal.
Accordingly, when the H-SYNC is supplied to one input terminal of the exclusive OR gate 26 via a horizontal sync signal terminal H SYNC as 1/ of FIG. 5A, and a sync signal supplied to the monitor by means of the sync signal discriminating portion 27 is determined as the sync on green signal as illustrated in FIG. 5A to be the low signal as 2/ of FIG. 5A and supplied to other input terminal of the exclusive OR gate 26, the output of the exclusive OR gate 26 is a signal of the high level as 3/ of FIG. 5A.
After the output of the exclusive OR gate 26 is supplied to the multivibrator 28, the output pulse duty of the multivibrator 28 is adjusted by the time constant (R, C) to generate the clamp signal triggered at the back porch of the sync signal as 4/ of FIG. 5A.
On the other hand, when the horizontal sync signal is supplied to one input terminal of the exclusive OR gate 26 via the horizontal sync signal terminal H SYNC as 1/ of FIG. 5B, and the sync signal supplied to the monitor by means of the sync signal discriminating portion 27 is determined as the separate sync signal shown in FIG. 5B to be the high signal as 2/ of FIG. 5B and supplied to other input terminal of the exclusive OR gate 26, the output of the exclusive OR gate 26 is a signal of the low level as 3/ of FIG. 5B.
In response to the output of the exclusive OR gate 26, the multivibrator 28 determines the duty of output pulses in view of the time constant by the capacitor C and resistor R connected to one side thereof, and generates the clamp signal triggered at the front porch of the sync signal as 4/ of FIG. 5B. At this time, the trigger position of the generated clamp signal of the multivibrator 28 is determined in accordance with the output signal level of the exclusive OR gate 26. In other words, if the output of the exclusive OR gate 26 is high, the clamp signal is triggered at the back porch; otherwise it is triggered at the front porch.
However, in the conventional clamp signal generation-control circuit shown in FIGS. 2 and 3 involves problems as below:
First, when the clamp signal is triggered at the front portion of the sync signal, an abnormal picture is displayed due to a difference between video reference levels if the sync on green signal and the sync signal via the H/V sync signal input terminal are simultaneously supplied.
Second, when the clamp signal is triggered at the back portion of the sync signal, if there is no margin (e.g., in V-7, VRAM2, etc.) between a blanking period of the sync signal, the clamp signal is mixed on the video signal portion to make the video signal portion be 0 V which inhibits the display of the picture.
Third, since the clamp signal must be manually switched for front-to-back shifting performed to trigger the clamp signal at the front or back portion of the sync signal, a nonprofessional user may be confused.
Moreover, in the conventional clamp signal-generation circuit of FIG. 4, if the separate sync signal is received into the monitor as illustrated in FIG. 5B, the timing of the clamp signal from the multivibrator 28 is improper owing to a delay time caused during the RGB composite video signal passing through a gate, etc., when a signal among the separate sync signal as in V-7, VRAM II, etc., having the sync timing same as a blanking timing is supplied. Thus, The clamp signal is generated at the composite video signal portion, so that the composite video signal portion goes to 0 V to induce a segment phenomenon due to the fact that the picture is not displayed.